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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">SPI TX FIFO Statuses<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__spi.html">SPI (SCB)</a> &raquo; <a class="el" href="group__group__scb__spi__macros.html">Macros</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Macros to check SPI TX FIFO status returned by <a class="el" href="group__group__scb__spi__low__level__functions.html#ga987fdbe86c1fbfbadfa51cdf82f84632">Cy_SCB_SPI_GetTxFifoStatus</a> function or assign mask for <a class="el" href="group__group__scb__spi__low__level__functions.html#gadf6044cb7d9567450502fec59537dad4">Cy_SCB_SPI_ClearTxFifoStatus</a> function. </p>
<p>Each SPI TX FIFO status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga09966d868419acdcc1b39a20e168437a"><td class="memItemLeft" align="right" valign="top"><a id="ga09966d868419acdcc1b39a20e168437a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__spi__macros__tx__fifo__status.html#ga09966d868419acdcc1b39a20e168437a">CY_SCB_SPI_TX_TRIGGER</a>&#160;&#160;&#160;(SCB_INTR_TX_TRIGGER_Msk)</td></tr>
<tr class="memdesc:ga09966d868419acdcc1b39a20e168437a"><td class="mdescLeft">&#160;</td><td class="mdescRight">The number of entries in the TX FIFO is less than the TX FIFO trigger level value. <br /></td></tr>
<tr class="separator:ga09966d868419acdcc1b39a20e168437a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02c11eee0328c4d9907fae3ce30f050c"><td class="memItemLeft" align="right" valign="top"><a id="ga02c11eee0328c4d9907fae3ce30f050c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__spi__macros__tx__fifo__status.html#ga02c11eee0328c4d9907fae3ce30f050c">CY_SCB_SPI_TX_NOT_FULL</a>&#160;&#160;&#160;(SCB_INTR_TX_NOT_FULL_Msk)</td></tr>
<tr class="memdesc:ga02c11eee0328c4d9907fae3ce30f050c"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TX FIFO is not full, there is a space for more data. <br /></td></tr>
<tr class="separator:ga02c11eee0328c4d9907fae3ce30f050c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac78e12f183e9dd8363763baf5c4694ab"><td class="memItemLeft" align="right" valign="top"><a id="gac78e12f183e9dd8363763baf5c4694ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__spi__macros__tx__fifo__status.html#gac78e12f183e9dd8363763baf5c4694ab">CY_SCB_SPI_TX_EMPTY</a>&#160;&#160;&#160;(SCB_INTR_TX_EMPTY_Msk)</td></tr>
<tr class="memdesc:gac78e12f183e9dd8363763baf5c4694ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TX FIFO is empty, note that there may still be data in the shift register. <br /></td></tr>
<tr class="separator:gac78e12f183e9dd8363763baf5c4694ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga56c1ac0eb0d0baf71c58eb2300aff979"><td class="memItemLeft" align="right" valign="top"><a id="ga56c1ac0eb0d0baf71c58eb2300aff979"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__spi__macros__tx__fifo__status.html#ga56c1ac0eb0d0baf71c58eb2300aff979">CY_SCB_SPI_TX_OVERFLOW</a>&#160;&#160;&#160;(SCB_INTR_TX_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga56c1ac0eb0d0baf71c58eb2300aff979"><td class="mdescLeft">&#160;</td><td class="mdescRight">An attempt to write to the full TX FIFO. <br /></td></tr>
<tr class="separator:ga56c1ac0eb0d0baf71c58eb2300aff979"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e3957a4dd326629e12a880b679369a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__spi__macros__tx__fifo__status.html#ga6e3957a4dd326629e12a880b679369a1">CY_SCB_SPI_TX_UNDERFLOW</a>&#160;&#160;&#160;(SCB_INTR_TX_UNDERFLOW_Msk)</td></tr>
<tr class="memdesc:ga6e3957a4dd326629e12a880b679369a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Applicable only for the slave mode.  <a href="#ga6e3957a4dd326629e12a880b679369a1">More...</a><br /></td></tr>
<tr class="separator:ga6e3957a4dd326629e12a880b679369a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga6e3957a4dd326629e12a880b679369a1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6e3957a4dd326629e12a880b679369a1">&#9670;&nbsp;</a></span>CY_SCB_SPI_TX_UNDERFLOW</h2>

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<div class="memproto">
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          <td class="memname">#define CY_SCB_SPI_TX_UNDERFLOW&#160;&#160;&#160;(SCB_INTR_TX_UNDERFLOW_Msk)</td>
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<p>Applicable only for the slave mode. </p>
<p>The master tried to read more data elements than available. </p>

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